View HUFA76504DK8T_279090.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HUFA76504DK8
Data Sheet June 2001
2.3A, 80V, 0.222 Ohm, Dual N-Channel, Logic Level UltraFET Power MOSFET [ /Title (HUF7 Packaging JEDEC MS-012AA 6400S BRANDING DASH K8) /Subject (60V, 0.072 1 2 Ohm, 3 4 4A, NChannel, Symbol Logic Level SOURCE1 (1) UltraFE GATE1 (2) Power MOSFET) /Author Features
* Ultra Low On-Resistance - rDS(ON) = 0.200, VGS = 10V - rDS(ON) = 0.222, VGS = 5V * Simulation Models - Temperature Compensated PSPICETM and SABER Electrical Models - Spice and SABER Thermal Impedance Models - www.Fairchildsemi.com * Internal RG = 50 * Peak Current vs Pulse Width Curve * UIS Rating Curve
DRAIN 1 (8) DRAIN 1 (7)
5
* Transient Thermal Impedance Curve vs Board Mounting Area
Ordering Information
DRAIN 2 (6) SOURCE2 (3) GATE2 (4) DRAIN 2 (5)
PART NUMBER HUFA76504DK8
PACKAGE MS-012AA
BRAND 76504DK8
NOTE: When ordering, use the entire part number. Add the suffix T to obtain the variant in tape and reel, e.g., HUFA76504DK8T.
/KeyAbsolute Maximum Ratings TA = 25oC, Unless Otherwise Specified words (Harris Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS SemiDrain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR conduc- Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS tor, N- Drain Current (T = 25oC, V = 5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I Continuous A GS D ChanContinuous (TA= 25oC, VGS = 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA= 100oC, VGS = 5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID nel, Continuous (TA= 100oC, VGS = 4.5V) (Figure 2) (Note 3). . . . . . . . . . . . . . . . . . . . . . . . ID Logic Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS Level UltraFE Power Dissipation (Note.2). .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .P.D Derate Above 25oC . . . Power MOSOperating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg NOTES: 1. TJ = 25oC to 125oC. 2. 50oC/W measured using FR-4 board with 0.76 in2 (490.3 mm2) copper pad at 1 second. 3. 228oC/W measured using FR-4 board with 0.006 in2 (3.87 mm2) copper pad at 1000 seconds.
HUFA76504DK8 80 80 16 2.3 2.5 1.1 1.1 Figure 4 Figures 6, 17, 18 2.5 20 -55 to 150 300 260
UNITS V V V A A A A
W mW/oC oC
oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ Reliability data can be found at: http://www.mtp.intersil.com/automotive.html. All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
(c)2001 Fairchild Semiconductor Corporation Rev. A, June 4, 2001
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. UltraFET(R) is a registered trademark of Fairchild Corporation. PSPICE(R) is a registered trademark of Cadence Corporation. SABER(c) is a registered trademark of Avanti corporation.
HUFA76504DK8
Electrical Specifications
PARAMETER OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVDSS IDSS IGSS VGS(TH) rDS(ON) ID = 250A, VGS = 0V (Figure 12) ID = 250A, VGS = 0V , TA = -40oC (Figure 12) Zero Gate Voltage Drain Current VDS = 75V, VGS = 0V VDS = 70V, VGS = 0V, TA = 150oC Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250A (Figure 11) ID = 2.5A, VGS = 10V (Figures 9, 10) ID = 1.1A, VGS = 5V (Figure 9) ID = 1.1A, VGS = 4.5V (Figure 9) THERMAL SPECIFICATIONS Thermal Resistance Junction to Lead Thermal Resistance Junction to Ambient RJL RJA Pad Area = 0.50 in2 (323 mm2) (Note 2) Pad Area = 0.027 in2 (17.4 mm2) (Figure 23) Pad Area = 0.006 in2 (3.87 mm2) (Figure 23) 25 50 191 228
oC/W oC/W oC/W oC/W
TA = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
80 70 -
-
1 250 100 3 0.200 0.222 0.230
V V A A nA
VGS = 16V
1 -
0.173 0.193 0.200
V
SWITCHING SPECIFICATIONS (VGS = 4.5V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time tON td(ON) tr td(OFF) tf tOFF tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(5) Qg(TH) Qgs Qgd CISS COSS CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 13) VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 40V, ID = 1.1A, Ig(REF) = 1.0mA (Figures 14, 19, 20) VDD = 40V, ID = 2.5A VGS = 10V, RGS = 47 (Figures 16, 21, 22) VDD = 40V, ID = 1.1A VGS = 4.5V, RGS = 43 (Figures 15, 21, 22) 27 40 73 31 100 160 ns ns ns ns ns ns
SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance 270 62 11 pF pF pF 6.6 3.4 0.3 0.8 1.4 10 5.4 0.5 nC nC nC nC nC 10 18 115 36 41 230 ns ns ns ns ns ns
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage SYMBOL VSD trr QRR ISD =1.1A ISD = 0.7A Reverse Recovery Time Reverse Recovered Charge
(c)2001 Fairchild Semiconductor Corporation
TEST CONDITIONS
MIN -
TYP -
MAX 1.25 1.00 62 115
UNITS V V ns nC
ISD = 5.0A, dISD/dt = 100A/s ISD = 5.0A, dISD/dt = 100A/s
Rev. A, June 4, 2001
HUFA76504DK8 Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) 3.0 2.5 VGS = 10V, RJA = 50oC/W 2.0 1.5 1.0 0.5 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (oC) 150
VGS = 4.5V, RJA = 228oC/W
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE
2 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM
THERMAL IMPEDANCE
RJA = 228oC/W
ZJA, NORMALIZED
0.1
0.01
t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-2 10-1 100 101 102 103
SINGLE PULSE 0.001 10-5 10-4 10-3 t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
200 100 IDM, PEAK CURRENT (A)
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION
RJA = 228oC/W
TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 150 - TA 125
VGS = 10V
10
VGS = 4.5V
1
10-5
10-4
10-3
10-2
10-1 t, PULSE WIDTH (s)
100
101
102
103
FIGURE 4. PEAK CURRENT CAPABILITY
(c)2001 Fairchild Semiconductor Corporation
Rev. A, June 4, 2001
HUFA76504DK8 Typical Performance Curves
200 100 ID, DRAIN CURRENT (A) SINGLE PULSE TJ = MAX RATED TA = 25oC
(Continued)
20 IAS, AVALANCHE CURRENT (A)
10
IfSTARTING TJ = 150oC R=0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] STARTING TJ = 25oC
10 100s
1
OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON)
1ms
STARTING TJ = 150oC
0.1 1
RJA = 228oC/W
10ms 200
1 0.01
0.1 tAV, TIME IN AVALANCHE (ms)
1
10 100 VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
10 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V ID, DRAIN CURRENT (A)
10 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC VGS = 4.5V
ID, DRAIN CURRENT (A)
8
8
6
6 VGS = 10V 4 VGS = 3.5V
4 TJ = 25oC 2 TJ = 150oC 0 2.0 2.5 3.0 3.5 4.0 VGS, GATE TO SOURCE VOLTAGE (V) 4.5 TJ = -55oC
2
VGS = 3V
0 0 1 2 VDS, DRAIN TO SOURCE VOLTAGE (V) 3
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
350 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) 300 ID = 2.5A 250
2.5
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 2.5A
2.0
1.5
ID = 1.1A 200
1.0
150 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10
0.5 -80
-40
0 40 80 120 TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
(c)2001 Fairchild Semiconductor Corporation
Rev. A, June 4, 2001
HUFA76504DK8 Typical Performance Curves
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE
(Continued)
1.2 ID = 250A
1.0
1.1
0.8
1.0
0.6 -80
-40
0 40 80 120 TJ, JUNCTION TEMPERATURE (oC)
160
0.9 -80
-40
0 40 80 120 TJ , JUNCTION TEMPERATURE (oC)
160
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
VGS , GATE TO SOURCE VOLTAGE (V)
1000 CISS = CGS + CGD C, CAPACITANCE (pF)
10 VDD = 40V 8
100 COSS CDS + CGD CRSS = CGD 10 VGS = 0V, f = 1MHz 3 0.1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 80
6
4 WAVEFORMS IN DESCENDING ORDER: ID = 2.5A ID = 1.1A 0 2 4 Qg, GATE CHARGE (nC) 6 8
2
0
NOTE: Refer to Application Notes AN7254 and AN7260. FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
80 VGS = 4.5V, VDD = 40V, ID = 1.1A td(OFF) SWITCHING TIME (ns) SWITCHING TIME (ns) 60
120 VGS = 10V, VDD = 40V, ID = 2.5A td(OFF)
80
40
tr tf
20
td(ON)
40
tf tr
0 0 10 20 30 40 RGS, GATE TO SOURCE RESISTANCE () 50
0 0 10 20 30 40 RGS, GATE TO SOURCE RESISTANCE ()
td(ON) 50
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
(c)2001 Fairchild Semiconductor Corporation
Rev. A, June 4, 2001
HUFA76504DK8 Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
VDS RL VDD VDS VGS = 10V VGS
+
Qg(TOT)
Qg(5) VDD VGS VGS = 1V 0 Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 5V
DUT Ig(REF)
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
VDD DUT 0
10% 90%
10%
RGS VGS VGS 0 10% 50% PULSE WIDTH 50%
FIGURE 21. SWITCHING TIME TEST CIRCUIT
FIGURE 22. SWITCHING TIME WAVEFORM
(c)2001 Fairchild Semiconductor Corporation
Rev. A, June 4, 2001
HUFA76504DK8 Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
P (T -T ) JM A = -----------------------------DM R JA 300 RJA = 103.2 - 24.3 250
* ln(AREA)
228 oC/W - 0.006in2 191 oC/W - 0.027in2
R, RJA (oC/W)
200 150 100 50
(EQ. 1)
R = 46.4 - 21.7 * ln(AREA)
0 0.001 0.01 0.1 1 AREA, TOP COPPER AREA (in2) PER DIE
In using surface mount devices such as the SOP-8 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of P DM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 23 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Displayed on the curve are RJA values listed in the Electrical Specifications table. The points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PDM. Thermal resistances corresponding to other copper areas can be obtained from Figure 23 or by calculation using Equation 2. RJA is defined as the natural log of the area times a cofficient added to a constant. The area, in square inches is the top copper area including the gate and source pads.
R JA = 103.2 - 24.3 x
FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA
While Equation 2 describes the thermal resistance of a single die, several of the new UltraFETTMs are offered with two die in the SOP-8 package. The dual die SOP-8 package introduces an additional thermal component, thermal coupling resistance, R. Equation 3 describes R as a function of the top copper mounting pad area.
R
= 46.4 - 21.7 x
ln ( Area )
(EQ. 3)
The thermal coupling resistance vs. copper area is also graphically depicted in Figure 23. It is important to note the thermal resistance (RJA) and thermal coupling resistance (R) are equivalent for both die. For example at 0.1 square inches of copper: RJA1 = RJA2 = 159C/W
R1 = R2 = 97C/W
TJ1 and TJ2 define the junction temerature of the respective die. Similarly, P1 and P2 define the power dissipated in each die. The steady state junction temperature can be calculated using Equation 4 for die 1and Equation 5 for die 2. Example: To calculate the junction temperature of each die when die 2 is dissipating 0.5 Watts and die 1 is dissipating 0 Watts. The ambient temperature is 70C and the package is mounted to a top copper area of 0.1 square inches per die. Use Equation 4 to calulate TJ1 and and Equation 5 to calulate TJ2.
.
T J1 = P 1 R JA + P 2 R + T A
(EQ. 4)
TJ1 = (0 Watts)(159C/W) + (0.5 Watts)(97C/W) + 70C TJ1 = 119C
T J2 = P 2 R JA + P 1 R + T A (EQ. 5)
ln ( Area )
TJ2 = (0.5 Watts)(159C/W) + (0 Watts)(97C/W) + 70C TJ2 = 150C
(EQ. 2)
(c)2001 Fairchild Semiconductor Corporation
Rev. A, June 4, 2001
HUFA76504DK8
The transient thermal impedance (ZJA) is also effected by varied top copper board area. Figure 24 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1.
160
IMPEDANCE (oC/W)
ZJA, THERMAL
120
COPPER BOARD AREA - DESCENDING ORDER 0.020 in2 0.140 in2 0.257 in2 0.380 in2 0.493 in2
80
40
0 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) 102 103
FIGURE 24. THERMAL RESISTANCE vs MOUNTING PAD AREA
(c)2001 Fairchild Semiconductor Corporation
Rev. A, June 4, 2001
HUFA76504DK8 PSPICE Electrical Model
.SUBCKT HUFA76504DK8 2 1 3 ;
CA 12 8 2.5e-10 CB 15 14 3e-10 CIN 6 8 2.6e-10
REV 18 January 2001
DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD
10
LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + EBREAK MWEAK MMED MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 14 IT 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 17 18 DBODY DRAIN 2 RSLC1 51 ESLC 50
RSLC2
5 51
ESG 6 8 + LGATE GATE 1 RLGATE EVTEMP RGATE + 18 22 9 20 EVTHRES + 19 8 6
IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 4.21e-10 LSOURCE 3 7 1.28e-10 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 1.1e-1 RGATE 9 20 5.74e1 RLDRAIN 2 5 10 RLGATE 1 9 42.1 RLSOURCE 3 7 12.8 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 5.72e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*12),3.7))} .MODEL DBODYMOD D (IS = 3.1e-13 N = 1.03 RS = 4.2e-2 TRS1 = 3e-4 TRS2 = 1.3e-6 CJO = 6.82e-10 TT = 3.3e-8 M = 0.8 XTI = 4) .MODEL DBREAKMOD D (RS = 1.65 TRS1 = 1e-3 TRS2 = -9e-6) .MODEL DPLCAPMOD D (CJO = 1.7e-10 IS = 1e-30 M = 0.85) .MODEL MMEDMOD NMOS (VTO = 2.2 KP = 1.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 5.74e1) .MODEL MSTROMOD NMOS (VTO = 2.56 KP = 18 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.94 KP = 0.04 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 5.74e2 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.12e-3 TC2 = -3e-7) .MODEL RDRAINMOD RES (TC1 = 9e-3 TC2 = 2e-5) .MODEL RSLCMOD RES (TC1 = 2.8e-3 TC2 = 1.9e-5) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -2e-3 TC2 = -3e-6) .MODEL RVTEMPMOD RES (TC1 = -1.5e-3 TC2 = 1e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -4 VOFF= -1) VON = -1 VOFF= -4) VON = -0.5 VOFF= 0.5) VON = 0.5 VOFF= -0.5)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
(c)2001 Fairchild Semiconductor Corporation
+
-
EBREAK 11 7 17 18 100.6 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1
RDRAIN 21 16
-
VBAT +
8 22 RVTHRES
Rev. A, June 4, 2001
HUFA76504DK8 SABER Electrical Model
REV 18 January 2001 template HUFA76504dk8 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (is = 3.1e-13, n1 = 1.03, rs = 4.2e-2, trs1 = 3e-4, trs2 = 1.3e-6, cjo = 6.82e-10, tt = 3.38e-8, m = 0.8, xti = 4) dp..model dbreakmod = (rs = 1.65, trs1 = 1e-3, trs2 = -9e-6) dp..model dplcapmod = (cjo = 1.7e-10, isl = 10e-30, n1 = 10, m = 0.85) m..model mmedmod = (type=_n, vto = 2.2, kp = 1.1, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.56, kp = 18, is = 1e-30, tox = 1) LDRAIN m..model mweakmod = (type=_n, vto = 1.94, kp = 0.04, is = 1e-30, tox = 1, rs = .1) DPLCAP 5 sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4, voff = -1) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1, voff = -4) 10 sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.5) RLDRAIN RSLC1 sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -0.5)
51 RDBREAK
DRAIN 2
c.ca n12 n8 = 2.5e-10 c.cb n15 n14 = 3e-10 c.cin n6 n8 = 2.6e-10 dp.dbody n7 n71 = model=dbodymod dp.dbreak n72 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 4.21e-10 l.lsource n3 n7 = 1.28e-10
GATE 1 RLGATE LGATE
RSLC2 ISCL
72 DBREAK 11 MWEAK
RDBODY
ESG + EVTEMP RGATE + 18 22 9 20 6 6 8 EVTHRES + 19 8
50 RDRAIN 21 16
71
DBODY
MMED MSTRO CIN 8
EBREAK + 17 18
RSOURCE
LSOURCE 7 RLSOURCE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
S1A S2A 14 13 S2B 13 + EGS 6 8 EDS CB + 5 8 14 15
SOURCE 3
res.rbreak n17 n18 = 1, tc1 = 1.12e-3, tc2 = -3e-7 res.rdrain n50 n16 = 1.1e-1, tc1 = 9e-3, tc2 = 2e-5 res.rgate n9 n20 = 5.74e1 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 42.1 res.rlsource n3 n7 = 12.8 res.rslc1 n5 n51 = 1e-6, tc1 = 2.8e-3, tc2 = 1.9e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 5.72e-2, tc1 = 1e-3, tc2 = 1e-6 res.rvtemp n18 n19 = 1, tc1 = -1.5e-3, tc2 = 1e-6 res.rvthres n22 n8 = 1, tc1 = -2e-3, tc2 = -3e-6 spe.ebreak n11 n7 n17 n18 = 100.6 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1
12
13 8 S1B
RBREAK 17 18 RVTEMP 19 IT
CA
VBAT +
-
-
8 RVTHRES
22
equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/12))** 3.7)) } }
(c)2001 Fairchild Semiconductor Corporation
Rev. A, June 4, 2001
HUFA76504DK8 SPICE Thermal Model
REV 18 January 2001 HUFA76504DK8 Copper Area = 0.38 in 2 CTHERM1 th 8 8.5e-4 CTHERM2 8 7 1.8e-3 CTHERM3 7 6 5.0e-3 CTHERM4 6 5 1.3e-2 CTHERM5 5 4 4.0e-2 CTHERM6 4 3 1.5e-1 CTHERM7 3 2 6.5e-1 CTHERM8 2 tl 3.0 RTHERM1 th 8 3.5e-2 RTHERM2 8 7 6.0e-1 RTHERM3 7 6 2 RTHERM4 6 5 8 RTHERM5 5 4 18 RTHERM6 4 3 20 RTHERM7 3 2 29 RTHERM8 2 tl 31
th JUNCTION
RTHERM1 8
CTHERM1
RTHERM2 7
CTHERM2
RTHERM3 6
CTHERM3
RTHERM4
CTHERM4 5
SABER Thermal Model
Copper Area = 0.38 in 2 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 = 8.5e-4 ctherm.ctherm2 8 7 = 1.8e-3 ctherm.ctherm3 7 6 = 5.0e-3 ctherm.ctherm4 6 5 = 1.3e-2 ctherm.ctherm5 5 4 = 4.0e-2 ctherm.ctherm6 4 3 = 1.5e-1 ctherm.ctherm7 3 2 = 6.5e-1 ctherm.ctherm8 2 tl = 3.0 rtherm.rtherm1 th 8 = 3.5e-2 rtherm.rtherm2 8 7 = 6.0e-1 rtherm.rtherm3 7 6 = 2 rtherm.rtherm4 6 5 = 8 rtherm.rtherm5 5 4 = 18 rtherm.rtherm6 4 3 = 20 rtherm.rtherm7 3 2 = 29 rtherm.rtherm8 2 tl = 31 }
RTHERM5
CTHERM5 4
RTHERM6 3
CTHERM6
RTHERM7 2
CTHERM7
RTHERM8
CTHERM8
tl
AMBIENT
TABLE 1. Thermal Models COMPONANT CTHERM6 CTHERM7 CTHERM8 RTHERM6 RTHERM7 RTHERM8 0.02 in2 9.0e-2 4.0e-1 1.4 39 42 48 0.14 in2 1.3e-1 6.0e-1 2.5 26 32 35 0.257 in2 1.5e-1 4.5e-1 2.2 20 31 38 0.38 in2 1.5e-1 6.5e-1 3 20 29 31 0.493 in2 1.5e-1 7.5e-1 3 20 23 25
(c)2001 Fairchild Semiconductor Corporation
Rev. A, June 4, 2001
MS-012AA
E E1 1 e 2
HUFA76504DK8
8 LEAD JEDEC MS-012AA SMALL OUTLINE PLASTIC PACKAGE
A A1
INCHES SYMBOL A A1 b c MIN 0.0532 0.004 0.013 0.0075 0.189 0.2284 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.244 0.1574
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 5.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 6.20 4.00 NOTES 2 3 4
D 6
D
b
E E1 e H
5
h x 45o
0.050 BSC 0.0099 0.016 0.0196 0.050
1.27 BSC 0.25 0.40 0.50 1.27
c
L NOTES:
L 0.060 1.52 0o-8o
0.004 IN 0.10 mm
1. All dimensions are within allowable dimensions of Rev. C of JEDEC MS-012AA outline dated 5-90. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.006 inches (0.15mm) per side. 3. Dimension "E1" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 0.010 inches (0.25mm) per side.
0.050 1.27 0.024 0.6
4. "L" is the length of terminal for soldering. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. Controlling dimension: Millimeter. 7. Revision 8 dated 5-99.
0.155 4.0 0.275 7.0 MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE-MOUNTED APPLICATIONS
1.5mm DIA. HOLE
4.0mm USER DIRECTION OF FEED 2.0mm 1.75mm
MS-012AA
12mm TAPE AND REEL
12mm
C L
8.0mm
40mm MIN. ACCESS HOLE 18.4mm COVER TAPE 13mm 330mm 50mm
GENERAL INFORMATION 1. 2500 PIECES PER REEL. 2. ORDER IN MULTIPLES OF FULL REELS ONLY. 3. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
12.4mm
(c)2001 Fairchild Semiconductor Corporation
Rev. A, June 4, 2001
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM
DISCLAIMER
FAST FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MICROWIRETM OPTOLOGICTM
OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER SMART STARTTM
STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET VCXTM
STAR*POWER is used under license
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. H3

▲Up To Search▲

Price & Availability of HUFA76504DK8T

	To Download HUFA76504DK8T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .